One conventional way to seal an IC chip in a package is to provide an LOC construction wherein a lead frame is affixed on the circuit-forming surface of the IC chip, for example as shown in FIGS. 28 and 29.
In FIGS. 28 and 29, a package for a LOC construction of, for example, a DRAM (dynamic RAM) is shown, with a large number of bonding pads 1 being arranged on a straight line in the center of the semiconductor integrated circuit (IC) chip 10. The power supply lines 42, 43, which are called bus bars, and a large number of signal lines 44, 45, are respectively arranged on both sides of this pad line, forming the lead frame 11 used for the LOC. This lead frame is formed from an iron-nickel alloy, a copper alloy, copper, or the like.
The bus bars 42, 43 are connected to the power supply Vss or Vcc, and the signal lines 44, 45 are used for the various signals such as the addresses A0 to A10, CAS, and RAS.
The connections between each bonding pad 1 and each wire is accomplished by means of the respective wire bonding by means of bonding wires 6, 7 on one side of the bonding pad line, and by bonding wires 8, 9 on the other side. In this case, the wires 7, 9 that connect the signal lines 44, 45 (specifically, the inner lead section) straddles on top of the bus bars 42, 43. Also, the entire body is sealed by means of a molding resin 18 (in FIG. 28, shown by the virtual line) consisting of an epoxy resin or the like, with the outer lead section 45a being led to the outside of this molding resin.
In the package for the IC chip 10 made in this manner, the lead frame 11 is affixed on top of the IC chip 10 (specifically, on top of the circuit forming surface) by means of the LOC construction; details are explained with FIG. 29.
First, with regard to the IC chip 10, for example, a passivation film (protective film) 13 comprising a laminated film of SiO.sub.2 and Si.sub.3 N.sub.4, for example, SiO.sub.2 and Si.sub.3 N.sub.4 is provided on one main face of the silicon substrate 12, bonding pads 1 are formed in the window sections of this passivation film and connected to the internal circuits of the IC chip 10, then a thermosetting polyimide protective film 14 is adhered on the entire surface, except for this bonding pad region.
A filler is contained in the molding resin 18 (for example, additional SiO.sub.2 for the purpose of reducing the thermal expansion coefficient), but because a filler made in this manner contains radioactive elements such as uranium and thorium, which radiate .alpha.-rays, the so-called soft errors are easily generated wherein the .alpha.-rays from these radioactive elements are irradiated on the IC chip 10 and the circuit operates erroneously. The polyimide protective film 14 in particular prevents the invasion of the .alpha.-rays generated in that manner, and is provided to prevent defects due to soft errors.
The process that forms the polyimide protective film 14 on top of the passivation film 13, which consists of the laminated film of Si.sub.3 N.sub.4 film 13A and SiO.sub.2 film 13B, is shown summarized in FIGS. 30-33.
First, after the passivation film 13 is selectively etched (FIG. 30) to expose the bonding pads 1, a noncured thermosetting polyimide resin 14A is coated on the entire surface (FIG. 31.
Next, an etching mask 20 is formed in the prescribed pattern by ultraviolet radiation and a developing process (FIG. 32). Using this mask 20, the polyimide resin 14A is wet etched, the bonding pads 1 are exposed (FIG. 33) and, after the removal of the mask 20, curing is performed, producing the polyimide protective film 14.
As shown in FIG. 29, frame 11 is adhered on top of the polyimide protective film 14 by means of the double-faced adhesive type of insulating tape 15 (but, in FIG. 28, the insulating tape 15 is omitted from the illustration). This insulating tape 15 is a tape wherein adhesives (for example, thermoplastic adhesives) 17, 19 are respectively painted on both faces of the insulating film substrate 16, lead frame 11 is adhered to the substrate 16 under heat and pressure by means of one of the adhesives 17, and the substrate 16 is adhered on top of the polyimide protective film 14 for the IC chip 10 under heat and pressure by means of the other adhesive 19. In this manner, the lead frame 11 is mounted and pressure bonded on top of the IC chip 10 by means of the insulating tape 15.
However, because the lead frame 11 is affixed on top of the IC chip 10 by means of the insulating tape 15, in addition to the thickness of the insulating film substrate 16 being, for example, 50 .mu.m, the thickness of the adhesives 17, 19 on both of its faces is, for example 12.5 .mu.m, respectively. Therefore, because the combined thickness of the insulating tape 15 becomes as much as 75 .mu.m (depending on the circumstances, 75 to 175 .mu.m), the fact is clear that the various defects (a) to (d) presented below are mainly generated.
(a) Breaks are generated in the metal wiring during the mounting pressure and temperature cycles.
During pressure mounting for the lead frame 11, the stress that is shown by the following formula is generated: ##EQU1## where Tm: temperature (.degree.C.) during mounting
-65.degree.: minimum temperature (.degree.C.) during the thermal cycle PA0 E: modulus of elasticity of the insulating tape including the adhesives PA0 .alpha..sub.2 : thermal expansion coefficient of the insulating tape including the adhesives PA0 .alpha..sub.1 : thermal expansion coefficient of the silicon substrate of the IC chip PA0 h: thickness (.mu.m) of the insulating tape including the adhesives PA0 W: width (.mu.m) of the insulating tape including the adhesives PA0 IR Reflow Test PA0 Thermal Cycle Test (-65-150.degree. C.) PA0 Soft Error PA0 Parasitic Capacitance PA0 t: polyimide thickness PA0 .epsilon.: polyimide dielectric rate (3.3) PA0 .epsilon..sub.0 : dielectric rate of vacuum PA0 C: capacitance PA0 Package Warpage PA0 X: warpage of wafer PA0 a: length of the arc of the warped wafer PA0 D: wafer thickness (280 .mu.m) PA0 E: Si (wafer) modulus of elasticity (16200 kg/mm.sup.2) PA0 t: polyimide resin film thickness PA0 v: Poisson ratio (0.3) PA0 Tensile Stress PA0 Adhesive Strength PA0 Curing conditions: temperature 350.degree. C. (2 h), 390.degree. C. (1 h) PA0 Atmosphere: N.sub.2 gas, air flow PA0 Plasma etching conditions: CHF.sub.3 /CF.sub.4, CF.sub.4, none PA0 Thermal-pressure bonding temperatures: 280, 310, 330, 370, 400.degree. C. PA0 Thermal-pressure bonding pressures: 3.0 kg/cm.sup.2, 6.0 kg/cm.sup.2 PA0 Thermal-pressure bonding times: 3 sec, 6 sec PA0 Glass Transition Point, Surface Roughness, & Surface Chemical Composition of Photosensitive Thermosetting Polyimide Resin PA0 Electrical Characteristics PA0 Thermosetting epoxy resin PA0 Photosensitive thermosetting polyimide resin
According to this equation for stress, if the thickness and the thermal expansion coefficient of the insulating tape 15 including the adhesives are large, the stress during the mounting pressure of the lead frame easily becomes large. In the case of the mounting pressure of the lead frame 11, because the insulating tape 15 is used, due to the thickness and thermal expansion coefficient of this insulating tape 15, as is shown in FIG. 34, cracks 23 are generated in the IC chip 10, particularly from the outer edge to the inner portion of the insulating tape 15, and there are instances in which the metal wiring 24 breaks.
(b) The generation of package cracks originating in the expansion of the insulating tape, which are generated during IR reflow.
At the time of affixing the completed IC package on top of the printed circuit wiring board 26, for example, as shown in FIG. 37, as a method of bonding the outer lead section 45a or 44a to the circuit pattern 27 by means of solder, there is the IR reflow method that conducts bonding by means of infrared ray (IR) heating. At the time of IR reflow, the IC package is heated to about 245.degree. C. at its peak.
Currently, the glass transition point (Tg) of the insulating tape is designed to be 210.degree. C. In order to prevent the oxidation of the lead frame 11, it is preferable that the temperature at which the lead frame 11 is glued to the chip 10 be made less than 400.degree. C., but it is necessary that this gluing temperature be above the glass transition temperature of the thermosetting adhesives 17, 19 of the insulating tape 15 +150.degree. C. It is for this reason that the glass transition point of the insulating tape 15 is designed to be 210.degree. C.
However, as for this glass transition point (210.degree. C.), since it is lower than the IR reflow temperature (245.degree. C.), as shown in FIG. 35, the adhesive makes the transition to a near liquid rubber condition during IR reflow, and its adhesive function is remarkably decreased. Due to this, during IR reflow, package cracks are easily generated.
On the other hand, because the combined thickness (75 .mu.m) of the insulating tape 15 is large, the percentage of moisture absorption of the tape itself (below 85.degree. C., 85% humidity) becomes as high as 2 to 2.5%. If the package is left to set for a long time in the air, the tape absorbs moisture, and as shown in FIG. 36, swelling is easily generated in the adhesives 17 and 19. This causes crack 25 to be generated in sealing resin 18 during IR reflow, and generates package cracks even more easily. It was confirmed that package cracks appeared in 16 out of 120 samples.
(c) Generation of package warpage.
As for the size of each section shown by A', B', C', D', B', F', H', I', and J' in FIG. 29, specifically, these are as shown in the following Table I. Here, these are shown for both a TSOP (Thin Small Outline Package) with a total thickness of about 1 mm (1000 .mu.m) and an SOJ (Single Outline J-Lead Package) with a total thickness of about 2.7 mm (2700 .mu.m).
TABLE I ______________________________________ 1 mm TSOP 2.7 mm SOJ ______________________________________ A' 0.195 mm (195 .mu.m) 0.810 mm (810 .mu.m) B' 0.125 mm (125 .mu.m) 0.200 mm (200 .mu.m) C' 0.075 mm (75 .mu.m) 0.075 mm (75 .mu.m) D' 0.010 mm (10 .mu.m) 0.010 mm (10 .mu.m) E' 0.280 mm (280 .mu.m) 0.280 mm (280 .mu.m) F' 0.325 mm (325 .mu.m) 1.335 mm (1335 .mu.m) H' 0.395 mm (395 .mu.m) 1.085 mm (1085 .mu.m) I' 0.325 mm (325 .mu.m) 1.335 mm (1335 .mu.m) J' 15.240 mm (15,240 .mu.m) 15.240 mm (15,240 .mu.m) ______________________________________
Because the thickness (C'=75 .mu.m) of insulating tape 15 is large, it is difficult to adopt a construction balance in the package. In particular, in the case of a TSOP package or the like with a 1 mm thickness, the bowing referred to as package warpage originating in the tape thickness (greater than 75 .mu.m) is easily generated.
In the 1-mm TSOP package used until now, it is difficult to make the resin thickness (A') on top of the lead frame less than 195 .mu.m, but this is because of the capabilities of the wire bonder and to prevent the protrusion of the wire loop outside the package. Because of this, when the IC chip thickness (B') is made 280 .mu.m, the resin thickness on top of the chip becomes H'=395 .mu.m and the resin thickness beneath the chip becomes I'=325 .mu.m. This unbalanced thickness relationship is naturally generated due to the insulating tape thickness being C'=75 .mu.m, and brings about the problem of package warpage.
Due to the generation of this type of package warpage, shown in exaggerated form in FIG. 37, the package is warped 30-60 .mu.m, the outer lead sections 45a or 44a on both edges in particular rise up in relation to the circuit pattern 27 on top of the printed wiring board 26, and there are instances when these do not connect.
(d) Cost increases.
Insulating tape 15 that adheres the lead frame 11 has a high value of above several tens of yen per single unit, the cost of packages using this rises, and there are limitations to its cost reduction.
Thus, the present applicants, to eliminate the types of defects, in Japanese Patent Application No. Hei 6[1994]-27367, proposed a semiconductor device and its manufacturing method (hereinafter, referred to as the invention of the previous application) for a package construction that can prevent the chip cracking and breakage of the wiring during the pressure bonded mounting and thermal cycles for the lead frame, that can control the package cracking and package warpage in processes such as IR reflow, and that can be manufactured at a low cost.
In other words, the invention of the previous application relates to a semiconductor device wherein a second protective film (in particular, a second protective film that alleviates the influence of the .alpha.-rays due to the filler of the molding resin) is provided on top of the protective film for the semiconductor chip, the lead frame is affixed on top of this second protective film, and this lead frame is electrically connected to the surface of the semiconductor chip, with the main components of the lead frame being affixed on top of the second protective film with a thermoplastic resin layer interposed and forming at least one portion of the second protective film.
In the semiconductor device of the invention of the previous application, the second protective film can be formed by means of a laminated body of a thermosetting polyimide resin layer, which becomes the bottom layer, and a thermoplastic polyimide resin layer, which becomes the upper layer.
In this case, in the laminated body, in the region wherein the lead frame is adhered, the thermoplastic polyimide resin layer and the thermosetting polyimide resin layer are formed in almost the same pattern. The thickness of the thermoplastic polyimide resin layer is 15-35 .mu.m, the thickness of the thermosetting polyimide resin layer is 10 to 30 .mu.m, and in the region where the lead frame is not adhered, the thickness of the thermosetting polyimide resin layer can be 5-15 .mu.m.
Also, in the laminated body, the thermoplastic polyimide resin layer can also be provided on top of the thermosetting polyimide resin layer in the regions where the lead frame is not adhered. The thickness of the thermoplastic polyimide resin layer can be 15-35 .mu.m, and the thickness of the thermosetting polyimide resin layer can be 10-30 .mu.m.
In either case, the total thickness of the laminated body within the lead frame adhesion regions can be 35 to 65 .mu.m.
In the semiconductor device of the invention of the previous application, the second protective layer can be made of only the thermoplastic polyimide resin layer.
In this case, the thickness of the thermoplastic polyimide resin layer can be 30-50 .mu.m. Also, it is preferable that the thermoplastic polyimide resin layer also be provided on top of regions where the lead frame is not adhered.
In the semiconductor device of the invention of the previous application, it is also permissible if the edges of the thermoplastic polyimide resin layer within the lead frame adhesion regions protrude 0.1 to 0.15 mm more than the edge of the lead frame (specifically, the width of the thermoplastic polyimide resin layer is made 0.1 to 0.15 mm larger on each side in relation to the width of the lead frame).
Also, the spacing between the cell section of the semiconductor chip and the edge of the thermoplastic resin layer can be 100 to 500 .mu.m on the side of the bonding pad for the semiconductor chip.
Also, the thermoplastic resin layer and/or the thermosetting resin layer can be present in the regions of the bonding pad.
As for the semiconductor device of the invention of the previous application, in actuality, the bonding pad and the lead frame are wire bonded, and the entire body can be sealed with a molding resin. Also, the lead frame can comprise the lead frame section used for the signal lines and the lead frame section used for the power-supply lines.
In the manufacture of the semiconductor device of the invention of the previous application, at least a thermoplastic resin is coated on top of the protective film for the semiconductor chip. This coated resin is patterned, and it is preferable that the lead frame be adhered on top of the thermoplastic resin layer after the curing is accomplished.
In this case, in practice, after the lead frame is adhered, the bonding pads of the semiconductor chip with the lead frame are wire bonded, then the entire body can be sealed with a molding resin.
Next, a concrete example of the invention of the previous application is explained based on FIGS. 38-46. This example is a device wherein the invention of the previous application was applied, for example, to a package for a DRAM, the same keys are applied to the components that are the same as in the prior example shown in FIGS. 28-37, so their explanations are omitted.
First, to explain the construction of the package of an LOC construction based on this example in FIGS. 38 and 39, the distinctive feature of this package is the fact that the thermoplastic polyimide resin layer 54 is laminated on top of the passivation film 13 of the IC chip 10. Using that thermoplasticity, the bus bars 42, 43 and the signal lines 44, 45 (inner lead section) of the lead frame 11 on top of this are bonded by thermal pressure (pressure-bonding mounted).
In other words, the thermoplastic polyimide resin layer 54 provided on top of the IC chip, along with functioning as a second protective film in the same manner as the previously mentioned polyimide protective film 14, is used as an adhesive for the lead frame 11, and the point at which the insulating tape 15 like that previously mentioned is not used is a fact that should be noted.
According to this example, as shown in FIGS. 38 and 39, the second protective layer is formed by means of only the thermoplastic polyimide resin layer 54. This resin layer 54 is provided across almost the entire region of the memory cell section of the IC, as shown by the diagonal lines in FIG. 39.
Also, it is preferable for the thickness (b) of the polyimide resin layer 54 to be 20-45 .mu.m. The glass transition point of the thermoplastic polyimide resin layer 54 should be 210.degree. C. The reason for this is that, in the same manner as presented above, the temperature at the time of thermal pressure bonding of the lead frame on the IC chip surface is less than 400.degree. C., with the wire bonding temperature being 200.degree. C.
Also, when looked at in regard to the entire body of the package, specifically, the size of each component can be designed as shown in the following Table II.
TABLE II ______________________________________ 1 mm TSOP 2.7 mm SOJ ______________________________________ A 0.195 mm (195 .mu.m) 0.810 mm (810 .mu.m) B 0.125 mm (125 .mu.m) 0.200 mm (200 .mu.m) b 0.030 mm (30 .mu.m) 0.030 mm (30 .mu.m) E 0.280 mm (280 .mu.m) 0.280 mm (280 .mu.m) F 0.370 mm (370 .mu.m) 1.380 mm (1380 .mu.m) H 0.350 mm (350 .mu.m) 1.040 mm (1040 .mu.m) I 0.370 mm (370 .mu.m) 1.380 mm (1380 .mu.m) J 15.240 mm (15,240 .mu.m) 15.240 mm (15,240 .mu.m) ______________________________________
As for the package based on this example, because it is a construction wherein the lead frame 11 is directly pressure-bonding-mounted on top of the thermoplastic polyimide resin layer 54 used as the protective film, the following effects (A)-(E) can be obtained.
(A) The metal wiring breaks that are generated after the pressure-bonded mounting and during the thermal cycles can be prevented.
Because the insulating tape used in the conventional mounting was a thickness of 75 to 175 .mu.m, the thermal stress was large, but because the thickness of the polyimide resin layer 54 is as little as 30-50 .mu.m, the tension stress can be lowered as much as 30% compared to the conventional type.
Specifically, in the package internal section, the maximum stress is concentrated in the chip surface region directly beneath the corner section (P) of the bus bar shown in FIG. 39. Due to this, the tensile stress exerts a harmful influence on the device characteristics. When the tensile stress on top of the chip surface was found during a thermal cycle of 150.degree. C. to -65.degree. C., in the structure of FIG. 38, a tensile stress of 2.90 kg/mm.sup.2 was shown. It can be seen that it decreased about 30%, compared to a tensile stress of 4.20 kg/mm.sup.2 in the construction of FIG. 29 based on the conventional example.
(B) The package cracks that tend to be generated during IR reflow can be prevented.
Accompanying the capability to reduce the volume of the adhesive layer (polyimide resin layer), since the percentage of water absorption is reduced, the generation of package cracks during IR reflow can be remarkably reduced or prevented. In this case, there were absolutely no package cracks for a sampling of 120 units.
(C) Package warpage can be prevented.
Specifically, in a 1-mm TSOP or the like, a balance of the resin thickness above and below the chip within the package is easily obtained due to the equilibrium between the thicknesses (H) and (I), and the package warpage can be made less than 20 .mu.m or sufficiently prevented.
(D) A cost reduction can be realized.
Compared to the cost of the insulating tape (attached to the lead frame) used until now, in the mounting construction based on this example, the [cost] per unit can be reduced to less than about 1/7 to 1/33.
(E) Soft errors can be effectively prevented.
By providing the thermoplastic polyimide resin layer 54 at a thickness of above 30 .mu.m across the entire region of the cell section, the cell section is physically shielded from the previously mentioned .alpha.-rays. Therefore, the .alpha.-rays radiated from the lead frame and the filler (SiO.sub.2 and the like) within the molding resin 18 are effectively shielded, and soft errors of the memory cell section can be prevented.
The thermoplastic polyimide resin 54 used here has the following physical values, and can be of the construction shown in FIG. 40.
Tensile strength 10 kg/mm.sup.2 (room temperature)
Tensile modulus of elasticity 280 kg/mm.sup.2 (room temperature)
Tensile coefficient of elongation 10% (room temperature)
Volume resistivity 6.3.times.10.sup.16 .OMEGA.-cm
Leakage current value 1.61.times.10.sup.-11 (A) (room temperature) 1.07.times.10.sup.-11 (A) (PCT after 500 h)
(The PCT (Pressure Coupler Test) test is one stress testing method wherein the body to be tested is placed at a pressure of 1 atm and at 121.degree. C., and the changes in various characteristics before and after that are observed.)
Pyrolysis temperature 520.degree. C.
Thermal expansion coefficient 4.3.times.10.sup.-5 (1/.degree.C.) (30-100.degree. C.)
Glass transition point 240.degree. C. (In the sample evaluation, those with the points of 160-300.degree. C. were also used.)
Moisture absorption rate 0.91% 22.degree. C., 60% RH)
Next, to explain the main processes of the manufacturing method for the package shown in FIG. 38, first, after the passivation film 13 is selectively etched to expose the bonding pads (FIG. 41), a noncured thermoplastic polyimide resin 54A is painted on the entire face (FIG. 42).
Next, an etching mask 20 of a photoresist is formed in the prescribed pattern by ultraviolet radiation and developing processes (FIG. 43). Using this mask 20, the polyimide resin 54A is wet etched and the bonding pads 1 are exposed (FIG. 44). After removal of the mask 20, the curing is performed, producing the polyimide protective film 54.
The package that is manufactured in this manner has the superior advantages, but it can be seen that there are still problems that must be alleviated. As for these problems, they are mainly generated in the etching process of the polyimide resin 54A shown in FIGS. 43 and 44, which are explained in detail in FIG. 44.
Namely, because the thermoplastic polyimide resin 54A is a non-photosensitive type (even though exposed, it is not made photosensitive), it would be ideal for the etching to be done at the same window size as mask 20 shown by the broken line in FIG. 45(A), but because it depends on wet etching, in actuality, overetching occurs as in FIG. 45(B). Due to this, there are instances wherein the polyimide resin 54 between adjacent bonding pads 1--1 is completely eliminated.
In the event that the thickness of the polyimide resin 54 is 20 .mu.m before curing 10 .mu.m thickness after curing) and the size of the bonding pad 1 is 100 .mu.m.times.100 .mu.m, the amount of overetching becomes as high as 20-30 .mu.m, the polyimide resin 54 between adjacent bonding pads 1--1 is easily removed by the etching, and the passivation film 13 is exposed.
As a result, when sealing is done by means of molding resin 18 as shown in FIG. 38, this molding resin (for example, a multipurpose type of epoxy resin) 18 comes in direct contact with the passivation film 13, but because the molding resin 18 has poor adhesion characteristics with the Si.sub.3 N.sub.4 film 13A of the passivation film 13, fissures are generated in the Si.sub.3 N.sub.4 film 13A by the stress due to heat, and become a cause of package cracking. The problems due to the overetching in this manner are also generated in the same manner even in the etching of the thermosetting polyimide resin 14A shown in FIGS. 32 and 33, and the same types of defects as the are created.
This invention should eliminate defects such as the, and its purpose is to offer a semiconductor device and its manufacturing method for a package construction that can prevent chip cracking and wiring breakage after the pressure-bonded mounting of the lead frame and during the thermal cycles, that controls the package cracking and package warpage in processes such as IR reflow and resin sealing, and that can be done at a low cost.